TMS320LF2407APGEA

Product Summary

The TMS320LF2407APGEA is a digital signal processor (DSP) controller. It offers the enhanced TMS320 DSP architectural design of the C2xx core CPU for low-cost, low-power, and high-performance processing capabilities. The device also offers an array of memory sizes and different peripherals tailored to meet the specific price/performance points required by various applications. Flash devices of up to 32K words offer a cost-effective reprogrammable solution for volume production. The 2TMS320LF2407APGEA provides a password-based “code security” feature which is useful in preventing unauthorized duplication of proprietary code stored in on-chip Flash/ROM.

Parametrics

Absolute maximum ratings: (1)Supply voltage range, VDD, PLLVCCA, VDDO, and VCCA (see Note 1): - 0.3 V to 4.6 V; (2)VCCP range: - 0.3 V to 5.5 V; (3)Input voltage range, VIN: - 0.3 V to 4.6 V; (4)Output voltage range, VO LF240xA: - 0.3 V to 4.6 V; (5)Output voltage range,VO LC240xA: - 0.3 V to 4.6 V; (6)Input clamp current, IIK (VIN < 0 or VIN > VCC): ± 20 mA; (7)Output clamp current, IOK (VO < 0 or VO > VCC): ± 20 mA; (8)Operating free-air temperature ranges, TA: A version: - 40℃ to 85℃; S version: - 40℃ to 125℃; (9)Junction temperature range, TJ (see Note 2): - 40℃ to 150℃; (10)Storage temperature range, Tstg (see Note 2): - 65℃ to 150℃.

Features

Features: (1)High-Performance Static CMOS Technology: 25-ns Instruction Cycle Time (40 MHz); 40-MIPS Performance; Low-Power 3.3-V Design; (2)Based on TMS320C2xx DSP CPU Core: Code-Compatible With F243/F241/C242; Instruction Set and Module Compatible With F240/C240; (3)Controller Area Network (CAN) 2.0B Module(LF2407A, 2406A, LF2403A); (4)Serial Communications Interface (SCI); (5)16-Bit Serial Peripheral Interface (SPI); (6)Phase-Locked-Loop (PLL)-Based Clock Generation; (7)Up to 40 Individually Programmable, Multiplexed General-Purpose Input/Output; (8)(GPIO) Pins; (9)Up to Five External Interrupts (Power Drive Protection, Reset, Two Maskable Interrupts); (10)Power Management: Three Power-Down Modes; Ability to Power Down Each Peripheral; (11)Independently; (12)Real-Time JTAG-Compliant Scan-Based Emulation, IEEE Standard 1149.1 (JTAG).

Diagrams